1. Field of the Invention
This invention relates to a method and apparatus for simulating the behavior of electrical circuits. In particular, the invention relates to a method and apparatus for simulating, on a computer, the behavior of electronic circuits having high speed, computationally intensive pipelined components for processing digital data.
2. Description of the Prior Art
Electrical circuit simulators have existed for many years as part of computer-aided circuit design systems. The circuit designer uses simulators to aid in the development of electrical circuits. The simulator models the behavior of a proposed circuit design, usually on a computer, without requiring the acquisition and interconnection of the particular discrete circuit components.
Some simulators allow the designer to analyze a high level functional model of the circuit, by computing the results of a particular set of processing operations on vectors of data elements, without regard for timing details such as whether data elements arrive at components in synchronization, or the time that the processing operations will take. This model is efficient to execute on a computer and is useful at the early stages of design.
Lower level simulation models provide the detailed timing analysis at the data element level which is necessary to verify that the circuit will actually work as desired and to determine how long it will take. A conventional simulator which provides details at the data element level normally operates at the data element level. In such simulators, a variable is used to indicate the current simulated time. All events which occur at this time are simulated before the time variable is advanced to the next time. The speed and capabilities of modern digital circuits make it very inefficient to simulate the behavior of such circuits in this manner, particularly on sequential processors.
In pipelined digital systems, signals representing discrete data elements flow through a sequence, or pipeline, of processing components in turn, being transformed at each stage. At any time, many different components are actively processing different data elements. Parallel paths in the circuit may also be active at the same time processing the same or different data elements. If a system simulates a pipelined system in the conventional manner, it simulates all of the processing of data elements which occurs at each component at a specific time. Then, it advances its time variable to the next simulated time and simulates the processing of the data elements which have been transformed at the previous times. The computational overhead of routing the data elements from each output of each component to the inputs of its successor components is incurred for each active component at each advance of simulated time. The simulator must determine the correct inputs to the correct successor components by searching the data structures which describe the circuit components and their connections.
The programming code to route the data elements from component to component in a conventional prior art simulator is substantially large compared to the code to simulate the actual processing of data elements. If data element routing is performed for each data element which is output from each active component, only a small fraction of computer processing time is spent replicating the processing of data elements. This inefficienoy can seriously degrade the performance and increase the effective costs of the simulation. For circuits having parallel pipelines of high speed, computationally intensive components, the costs and elapsed time of such a simulation process limits its effectiveness as a design aid.